The present invention relates to semiconductor technologies, and more particularly to manufacturing techniques of a type of semiconductor devices.
Through silicon via (TSV) technology is one of the key technologies for three dimensional (3D) packaging. TSV is the latest technology for chip-to-chip interconnects by manufacturing vertical conductions between chips or between wafers. Differing from conventional IC stacking technologies using package bonds or bumps, TSV can achieve maximum 3D packing density and minimum physical dimension, and greatly improve the performance of the chips in speed and power consumption.
Based on the stage of the manufacturing process at which a TSV process is performed, TSV manufacturing processes can be categorized as via-first, via-middle and via-last, wherein via-first is the process of etching TSV on a blank silicon wafer before manufacturing CMOS; via-middle is the process of etching TSV after manufacturing CMOS but before the back end of line (BEOL) process; and via-last is the process of etching TSV on the back side of a thinned wafer after the BEOL process.
Typically, a via-middle process includes TSV etching, copper (Cu) plating and filling, mechanical polishing, deposition of metal wiring layer Ml, and BEOL, after contact via (CT) etching, filling and mechanical polishing. This method introduces TSV process before depositing metal wire layer Ml, can achieve a better integration with various processes in the Fab, and is the most commonly used method in the industry.
Current via-middle processes commonly use metals with high conductivity, such as Cu, as TSV filling material. However, the thermal expansion coefficient of copper is 7.4 times of that of silicon, resulting in a large stress mismatch, especially after copper metal filling, and before and after the chemical mechanical polishing process on the copper layer, during which the stress may change dramatically, causing cracks between the TSV and the substrate as shown in FIG. 1. The presence of cracks allows the copper metal to diffuse into the substrate, resulting in greatly increased leakage and hence serious reliability problems. Therefore, the inventors have determined that how to slowly release stress, prevent cracks in silicon vias and thus, reduce wafer acceptance test (WAT) leakage is a problem to be solved at present time.